1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having a MOS transistor formed on a semiconductor substrate to form a desired device and a structure thereof.
2. Description of Related Art
At present, in the case of forming a MOS transistor on a semiconductor substrate to form a desired device, there are problems and requirements such as following (1) to (3) as regards microfabrication of a semiconductor device.
(1) In the case of forming a high-performance MOS transistor, it is preferable that an LDD (Lightly Doped Drain) structure be applied to a source/drain area, or that a contact plug be formed on a gate electrode by self align in a subsequent manufacturing process. This requires a side wall insulating film provided on a side surface portion of the gate electrode and a cap insulating film to protect a top surface of the gate electrode. As a result, the total film thickness from the surface of a semiconductor substrate to the top surface of the gate electrode becomes twice as much as the film thickness of only the conductor portion of the gate electrode, or more, when the gate electrode is formed.
In a configuration like this, problems of processing occur due to processing a gate electrode with a large film thickness when a width of the gate electrode itself and a space between the gate electrode and a gate electrode adjacent thereto become smaller as the progress of mircofabrication. Specifically, there are problems in which the shape of the gate electrode worsens at the time of etching, the margin of an etching decreases when the opening portion of a self-align contact is formed, a void is generated at the time of implantation into a space portion between gate electrodes of an interlayer dielectric film, or the like. These are obstructions that inhibit making further progress towards microfabrication.
(2) On the other hand, a trench-gate transistor for suppressing a short channel effect in respond to microfabrication of a MOS transistor is known (see Japanese Patent Laid-Open No. 2007-123551). In a method for manufacturing the MOS transistor, after a device isolation area is formed on a semiconductor substrate, the semiconductor substrate (for example, a Si substrate) is etched to form a trench for a gate electrode. Because of this, it is effective for solving problem (1).
However, if the gate electrode cuts across the device isolation area, a conductive film for securing conduction of the gate electrode needs to be formed separately on the device isolation area because the trench is not formed on the device isolation area. The conductive film separately formed comes in contact with the top surface of the gate electrode that is filled in the trench portion so that a pattern of the gate electrode is formed. Because of this, there is a problem in which a conductor is likely to remain at the boundary portion of the inside and the outside of the device isolation area when the conductive film that has been separately formed is etched, resulting in the possibility of an electrical short circuit. Accordingly, an easier manufacturing method is required when the trench-gate transistor is used in order to progresses microfabrication.
(3) In general, a channel area and a diffusion layer area functioning as a source/drain area are formed by the same pattern in an active area in which a MOS transistor is formed. Thus, in the case of, for example, a DRAM memory cell, it is necessary to arrange rectangular patterns that have a high aspect ratio as an active area. Since a corner portion of the active area becomes rounded because of a characteristic of a lithography process at the time of the pattern formation, there are problems that a contact area with a contact plug decreases, or margin to alignment deviation cannot be sufficiently secured when the contact plug is formed. These are obstructions that inhibit making further progress toward microfabrication.
Additionally, Japanese Patent Laid-Open No. 2006-261625 is mentioned, for example, as a related art relative to the problem (2). In this patent document, after a polysilicon layer that is in contact with an impurity diffusion layer is formed, the device isolation area and further an interlayer dielectric film are formed to form a trench gate electrode. While this technique is effective for solving problem (2), problems (1) and (3) cannot be solved by applying this technique.